Journal of Parallel and Distributed Computing - Elsevier.

For server-based environments, the operating system is a crucial component of the workload. Previous research suggests that database systems spend 30 to 40 percent of their execution time in the kernel (4), and our measurements show that the Apache Web server spends over 75% of its time in the kernel.

Research article Full text access Reduction of task migrations and preemptions in optimal real-time scheduling for multiprocessors by using dynamic T-L plane Ngoc-Son Pham, Youngmin Kim, Kwang-Hyun Baek, Chan-Gun Lee.

This course provides an introduction to parallel computing with a particular focus on chip-multiprocessors. The course begins by examining the potential advantages of multi- and many-core processors. It explores the basics of parallel algorithm design, approaches to parallel programming and the architecture of modern chip-multiprocessors.

Final version of CACM Research Highlights paper, May 17, 2010 x86-TSO: A Rigorous and Usable Programmer’s Model for x86 Multiprocessors Peter Sewell University of Cambridge Susmit Sarkar University of Cambridge Scott Owens University of Cambridge Francesco Zappa Nardelli INRIA Magnus O. Myreen University of Cambridge.

Multiprocessing Multiprocessing is a good way to optimize system performance in a computer. This is done by increasing the total number of CPU’s. When there are multiple CPU’s are located in a single circuit, this is known as multicore processor.

Chip Multiprocessors (CMPs) are flexible, high-frequency platforms on which to support Thread-Level Speculation (TLS). However, for TLS to deliver on its promise, CMPs must exploit multiple sources of speculative task-level parallelism, including any nesting levels of both subroutines and loop iterations. Unfortunately, these environments are hard to support in decentralized CMP hardware.

We propose and evaluate empirically the performance of a dynamic processor scheduling policy for multiprogrammed, shared memory multiprocessors. The policy is dynamic in that it reallocates processors from one parallel job to another based on the currently realized paralelism of those jobs.

Research Paper ENERGY EFFICIENCY IMPROVEMENT FOR 3-D CHIP MULTIPROCESSORS WITH NUCA ARCHITECTURE D.Priya, J.Arunarasi, S.Leo Pauline, J.Jenisha Address for Correspondence Department of ECE, Vel Tech Multitech, Avadi, Chennai-54, TamilNadu, India; ABSTRACT The (CMPs) chip multi processors is considered by uniform cache access (UCA) architecture.

This paper is a survey of cache coherence mechanisms in shared memory multiprocessors. Cache coherence is important to insure consistency and performance in scalable multiprocessors. A variety of hardware and software protocols have been proposed and investigated in simulation studies. Our.

In this paper, we employ these optimal algorithms to address the important issue of fault tolerance for scheduling general graphs. The input precedence graphs are augmented into Interval Orders and then scheduled optimally while incorporating fault tolerance measures.

Research Papers Following are PostScript files containing papers by the research group of Vipin Kumar organized by topics. Data Mining; Graph Partitioning; Parallel Solution of Sparse Linear System of Equations; N-Body Computation and Dense Linear System Solvers; Scalability Analysis; Linear Programming; Parallel Tree Search and Load Balancing.

The available commodity chip multiprocessors can be di- vided into two groups: a “fat camp” and a “lean camp”(12). Fat camp multiprocessors have a few wide issue, out-of-order cores with relatively high clock rates. These cores resemble uniprocessors and often share a large L2 cache.